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I was working on some EPLD code at work today, and had to hop on the internet to learn how to setup constraints in verilog. I was quite surpised to find the following example on the Xilinx website: Yes, the "//" (double front-slash) in front of the constraint would typically indicate a single line comment in the code. Could this perhaps be a typo?

I rooted around a somewhat out-of-date verilog syntax specification for a hint of proof that comments truely were parsed in the verilog grammar. A few more google searches later and I stumbled into a Xilinx page about Verilog Meta Comments.

Apparently, the Verilog parser actually parses comments in search of these meta comments. The Xilinx page mentioned that Verilog does not have a direct attribute definition while VHDL does. Without doing more research on this, it almost looks like the meta comments were a work-around to allow Verilog users to port their design constraints to VHDL.

The only other program I know that parses comments is Doxygen. Doxygen is a piece of software that parses comments and uses them automatically generate documentation for your code. It parses the code (comments) separately from the compiler, so doesn't really fall into the unusual category of meta comments.

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